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asahi kasei [AK4706] ms0507-e-00 2006/05 - 1 - general description the AK4706 offers the ideal features for digital set-t op-box systems. using akm's multi-bit architecture for its modulator, the AK4706 delivers a wide dynam ic range while preserving linearity for improved thd+n performance. the AK4706 int egrates a combination of scf and ctf filters, removing the need for high cost external filters and increasing perform ance for systems with excessive clock jitter. the AK4706 also including the audio switches, volumes, video switches, hd/sd video filters, etc. designed primarily for digital set-top-box systems with scart routing. the AK4706 is offered in a space saving 64-pin lqfp package. features ? dac sampling rates ranging from 8khz to 50khz 64db high attenuation 8x fir digital filter 2nd order analog lpf on chip buffer with single-ended output digital de?emphasis for 32k, 44.1k and 48khz sampling i/f format: 24bit msb justified, i 2 s, 18/16bit lsb justified master clock: 256fs, 384fs high tolerance to clock jitter ? analog switches audio section thd+n: ?86db (@2vrms) dynamic range: 96db (@2vrms) stereo analog volume with pop-noise free circuit: +6db to ?60db & mute analog inputs two stereo inputs (tv&vcr scart) one stereo input (changeover to internal dac) analog outputs two stereo outputs (tv, vcr scart) one mono output (modulator) pop noise free circuit for power on/off video section integrated lpf sd: ?40db@27mhz hd: ?40db@74.25mhz or 54mhz or 27mhz selectable 75ohm driver 6db gain for outputs adjustable gain four cvbs/y inputs (encx2, tv, vcr), three cvbs/y outputs (rf, tv, vcr) three r/c inputs (encx2, vcr), two r/c outputs (tv, vcr) three g and b inputs (enc, vcr, hd), two g and b outputs (tv, hd) bi-directional control for vcr-red/chroma ypbpr option (to 6mhz) vcr input monitor loop?through mode for standby auto?startup mode for power saving scart pin#16(fast blanking), pin#8(slow blanking) control s1/s2 dc control 2ch 24bit dac with av switch & hd/sd video filte r AK4706
asahi kasei [AK4706] ms0507-e-00 2006/05 - 2 - ? ak4702/05 software compatible ? power supply 5v+/?5% and 12v+/?5% low power dissipation / low power standby mode ? package small 64pin lqfp tvoutl monoout tvoutr vcroutl vcroutr +6 to -60db (2db/step) -6db/0db/ +2.44/+4db tvinl tvinr vcrinl vcrinr da c mclk bick lrck sdti bias (mute) volume #0 volume #1 tv1/0 vol mono sck sda register control pdn dvcom pvcom vcr1/0 vd1 vd2 vp vmono vss1 vss2 audio block(dapd=?0?) tvoutl monoout tvoutr vcroutl vcroutr +6 to -60db (2db/step) tvinl tvinr vcrinl vcrinr (nc) dacl dacr (nc) bias (mute) volume #1 tv1/0 vol mono sck sda register control pdn dvcom pvcom vcr1/0 vmono 0db/+6db volume #2 vd1 vd2 vp vss1 vss2 audio block(dapd=?1?)
asahi kasei [AK4706] ms0507-e-00 2006/05 - 3 - tvrc (enc g/cvbs) (vcr g) tvg (enc b/pb) (vcr b/pb) tvb tvvout rfv 6db 6db 6db 6db 0, 1, 2, 3db (enc r/c/pr) (enc c) (vcr r/c/pr) vcrvout vcrc 6db 6db (enc cvbs/y) (enc y) (vcr cvbs/y) (tv cvbs) encg vcrg encb vcrb encrc encc vcrrc enc v enc y vcrvin tvvin ( typical connection ) rf mod tv scart vcr scart ( typical connection ) vvd1 vvd2 vvd3 vvd4 6db mon hdpr 6db hdy 6db hdpb 6db ypbpr/rgb encpr ency2 encpb (enc r/pr) (enc g/y) (enc b/pb) vvss1 vvss2 vvss3 vvss4 video block
asahi kasei [AK4706] ms0507-e-00 2006/05 - 4 - monitor (vcr fb) tvfb driver 0/2.2/5v 0/4v tvsb vcrsb 0/6/12v 0/ 6/ 12v vcrfb ( typical connection ) tv scar t vcr scart ( typical connection ) int 0/2.2/5v video blanking block
asahi kasei [AK4706] ms0507-e-00 2006/05 - 5 - ? ordering guide AK4706vq -10 +70 c 64pin lqfp (0.5mm pitch) ? pin layout vcrvout 1 tvg 64 2 tvfb 3 vcrc 4 vvss2 5 tvvout 6 7 vvd2 8 tvrc 9 tvb 10 vvss1 11 nc 63 vvss3 62 nc 61 vvd4 60 nc 59 vvss4 58 57 56 5 5 54 encv 17 ency 18 tvvin 19 vcrvin 20 vcrfb 21 vcrrc 22 vcrg 23 vcrb 24 25 26 27 47 46 45 44 43 42 41 40 39 38 37 AK4706vq top view refi 12 28 48 vd2 53 hdy 13 hdpr 14 hdpb 15 vvd3 16 rfv 29 30 31 32 36 35 34 33 tvsb vcrsb int vss1 vd1 52 51 vss2 50 49 dvcom vp vcroutl vcroutr vcrinr tvinl monoout tvoutl tvoutr tvinr vcrinl pvcom pdn sda scl lrck sdti bick mclk vvd1 ency2 encpr encpb encb encg encrc encc ? main difference between ak4705 and AK4706 items ak4705 AK4706 hd video driver, filter - x s1/s2 chroma dc detector/generator - x package 48lqfp 64lqfp -: not available. x: available
asahi kasei [AK4706] ms0507-e-00 2006/05 - 6 - pin/function no. pin name i/o function 1 hdy o green/y output pin 2 hdpr o red/pr output pin 3 hdpb o blue/pb output pin 4 vvd3 - video power supply pin #3. 5v. normally connected to vvss3 with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 5 rfv o composite output pin for rf modulator 6 vcrvout o composite/luminance output pin for vcr 7 tvfb o fast blanking output pin for tv 8 vcrc o chrominance output pin for vcr 9 vvss2 - video ground pin #2. 0v. 10 tvvout o composite/luminance output pin for tv 11 vvd2 - video power supply pin #2. 5v. normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 12 tvrc o red/chrominance/pr output pin for tv 13 tvg o green/y output pin for tv 14 tvb o blue/pb output pin for tv 15 vvss1 - video ground pin #1. 0v. 16 refi o video current reference setup pin normally connected to vvd1 through a 10k ? 1% resistor externally. 17 vvd1 - video power supply pin #1. 5v. normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 18 ency2 i green/y input pin for encoder 19 encpr i red/chrominance/pr input pin for encoder 20 encpb i blue/pb input pin for encoder 21 encb i blue/pb input pin for encoder 22 encg i green/y input pin for encoder 23 encrc i red/chrominance/pr input pin for encoder 24 encc i chrominance input pin for encoder 25 encv i composite/luminance input1 pin for encoder 26 ency i composite/luminance input2 pin for encoder 27 tvvin i composite/luminance input pin for tv 28 vcrvin i composite/luminance input pin for vcr 29 vcrfb i fast blanking input pin for vcr 30 vcrrc i red/chrominance/pr input pin for vcr 31 vcrg i green/y input pin for vcr 32 vcrb i blue/pb input pin for vcr 33 int o interrupt pin for video blanking normally connected to vd(5v) through 10k ? resistor externally. 34 vcrsb i/o slow blanking input/output pin for vcr 35 tvsb o slow blanking output pin for tv 36 vcrinr i rch vcr audio input pin 37 vcrinl i lch vcr audio input pin 38 tvinr i rch tv audio input pin 39 tvinl i lch tv audio input pin 40 vcroutr o rch vcr audio output pin 41 vcroutl o lch vcr audio output pin 42 tvoutr o rch tv audio output pin 43 tvoutl o lch tv audio output pin
asahi kasei [AK4706] ms0507-e-00 2006/05 - 7 - pin/function (continued) 44 monoout o mono analog output pin 45 vp - power supply pin. 12v. normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 46 dvcom o dac common voltage pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 47 pvcom o audio common voltage pin normally connected to vss1 with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. the caps affect the settling time of audio bias level. 48 vss1 - ground pin. 0v. 49 vss2 - ground pin. 0v. 50 vd1 - power supply pin. 5v. normally connected to vss2 with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 51 vd2 - power supply pin. 5v. normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. mclk i master clock input pin at dapd= ?0?. 52 (nc) - no connect pin at dapd=?1?. this pin should be open. bick i audio serial data clock pin at dapd= ?0?. 53 dacr i rch analog audio input pin at dapd= ?1?. sdti i audio serial data input pin at dapd= ?0?. 54 (nc) - no connect pin at dapd= ?1?. this pin should be open. lrck i l/r clock pin at dapd= ?0?. 55 dacl i lch analog audio input pin at dapd= ?1?. 56 scl i control data clock pin 57 sda i/o control data pin 58 pdn i power-down mode pin when at ?l?, the AK4706 is in the power-down mode and is held in reset. the AK4706 should always be reset upon power-up. 59 vvss4 - video ground pin #4. 0v. 60 nc - no connect pin. this pin should be connected to vss1. 61 vvd4 - video power supply pin #4. 5v. normally connected to vvss3 with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 62 nc - no connect pin. this pin should be connected to vss1. 63 vvss3 - video ground pin #3. 0v. 64 nc - no connect pin. this pin should be connected to vss1.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 8 - ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog hdy, hdpr, hdpb, vcrc, tvvout, tvrc, tvg, tvb, ency2, encpr, encpb, encb, encg, encrc, encc, encv, ency, tvvin, vcrvin, vcrrc, vcrg , vcrb, vcrinr, vcrinl, tvinr, tvinl, vcroutr, vcroutl, tvoutr, tvoutl, monoout, dacr, dacl, rfv, vcrvout these pins should be open. vcrsb (o), tvfb, tvsb these pins should be open. digital vcrfb, vcrsb (i), mclk, bick, sdti, lrck, scl, sda, int these pins should be connected to vss2.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 9 - internal equivalent circuits pin no. pin name type equivalent circuit description 52 53 54 55 56 58 mclk bick sdti lrck scl pdn digital in (dapd="0") analog in (dapd="1") vd2 200 vss2 (60k) the 60k ? is attached only for bick pin and lrck pin. 57 sda digital i/o vd2 vss2 200 i2c bus voltage must not exceed vd2. 33 int digital out v ss1 vvd1 normally connected to vvd1(5v) through 10k ? resistor externally. 5 6 7 8 10 12 13 14 rfv vcrout tvfb vcrc tvvout tvrc tvg tvb video out vvd1 vvss1 vvd2 vvss2 1 2 3 hdy hdpr hdpb video out vvd4 vvss4 vvd3 vvss3 16 refi refi in vvd1 vvss1 200 normally connected to vvd1 through a 10k ? 1% resistor.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 10 - pin no. pin name type equivalent circuit description 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ency2 encpr encpb encb encg encrc encc encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb video in vvd1 200 vvss1 34 35 vcrsb tvsb video sb vp vss1 vp vss1 vss1 200 (120k) the 120k ? is not attached for tvsb pin and sdc bit = ?h?. 36 37 38 39 vcrinr vcrinl tvinr tvinl audio in vp 150k vss1 40 41 42 43 44 vcroutr vcroutl tvoutr tvoutl monoout audio out vp vss1 vp vss1 100 46 47 dvcom pvcom vcom out vd1 vss1 vd1 vss1 100 vd1 vss1
asahi kasei [AK4706] ms0507-e-00 2006/05 - 11 - absolute maximum ratings (vss1=vss2=vvss1=vvss2=vv ss3=vvss4=0v;note 1) parameter symbol min max units power supply vd1 vd2 vvd1 vvd2 vvd3 vvd4 vp |vss1-vvss4| (note 2) |vss1-vvss3| (note 2) |vss1-vvss2| (note 2) |vss1-vvss1| (note 2) |vss1-vss2| (note 2) -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 - - - - - 6.0 6.0 6.0 6.0 6.0 6.0 14 0.3 0.3 0.3 0.3 0.3 v v v v v v v v v v v v input current (any pins except for supplies) iin - 10 ma input voltage (note 3) vind -0.3 vd2+0.3 v video input voltage (note 4.) vinv -0.3 vvd1+0.3 v audio input voltage (except dacl/r pins) vina -0.3 vp+0.3 v audio input voltage (dacl/r pins) vina -0.3 vd2+0.3 v ambient operating temperature ta -10 70 c storage temperature tstg -65 150 c note 1.all voltages with respect to ground. note 2.vss1, vss2, vvss1, vvss2, vvss3 and vvss4 mu st be connected to the same analog ground plane. note 3.mclk, bick, sdti, lrck, scl, pdn pins note 4.ency2, encpr, encpb, encb, encg, encrc, encc, encv, en cy, tvvin, vcrvin, vcrfb, vcrrc, vcrg, vcrb pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=vvss1=vvss2=vv ss3=vvss4=0v; note 1) parameter symbol min typ max units power supply (note 5) vd1 vd2 vvd1 vvd2 vvd3 vvd4 vp 4.75 4.75 4.75 4.75 4.75 4.75 11.4 5.0 5.0 5.0 5.0 5.0 5.0 12 5.25 vd1 5.25 vvd1 vvd1 vvd1 12.6 v v v v v v v note 5. analog output voltage scales with the voltage of vd1. aout (typ@0db) = 2vrms vd1/5. the vvd1 and vvd2 must be the same voltage. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 12 - electrical characteristics (ta = 25 c; vp=12v, vd1=vd2=5v; vvd1=vvd2=vvd3=vvd4=5v; fs = 48khz; bick = 64fs) power supplies parameter min typ max units power supply current normal operation (pdn pin = ?h?; note 6) vd1+vd2 vvd1+vvd2+ vvd3+vvd4 vd1+vd2+ vvd1+vvd2+ vvd3+vvd4 vp power-down mode (pdn pin = ?l?; note 7) vd1+vd2 vvd1+vvd2+ vvd3+vvd4 vp 17 90 6 10 10 10 150 12 100 100 100 ma ma ma ma a a a note 6. stby bit = ?l?, all video outputs are active. no signal, no load for a/v switches. fs=48khz ?0?data input for dac. note 7. all digital inputs including clock pins (mclk, bick and lrck) are held at vd2 or vss2. digital characteristics (ta = 25 c; vd1=vd2= 4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.0 - - - - 0.8 v v low-level output voltage (sda pin: iout= 3ma, int pin: iout= 1ma) vol - - 0.4 v input leakage current iin - - 100 a
asahi kasei [AK4706] ms0507-e-00 2006/05 - 13 - analog characteristics (audio) (ta = 25 c; vp=12v, vd1=vd2=5v; vvd1=vvd2=vvd3=vvd4=5v; fs = 48khz; bick = 64fs; signal frequency = 1khz; 24bit input data; measurement frequency = 20hz 20khz; r l 4.5k ? ; volume #0=volume #1=0db, 0db=2vrms output; unless otherwise specified) parameter min typ max units dac resolution 24 bit analog input: (tvinl/tvinr/vcrinl/vcrinr pins) analog input characteristics input voltage 2 vrms input resistance 100 150 - k ? analog input: (dacl/dacr pin) analog input characteristics input voltage 1 vrms input resistance 40 60 - k ? stereo/mono output: (tvoutl/tvoutr/vcroutl/vcrout r/monoout pins; note 8) analog output characteristics volume#0 gain (dapd bit =?0?) (dvol1-0 = ?00?) (dvol1-0 = ?01?) (dvol1-0 = ?10?) (dvol1-0 = ?11?. note 9) - - - - 0 -6 +2.44 +4 - - - - db db db db volume#2 gain (dapd bit =?1?) (dvol1-0 = ?00?) (dvol1-0 = ?01?) 5.3 -0.7 6.0 0 6.7 0.7 db db volume#1 step width (+6db to ?12db) (-12db to ?40db) (-40db to ?60db) 1.6 0.5 0.1 2 2 2 2.4 3.5 3.9 db db db thd+n (at 2vrms output. note 10) ( at 3vrms output. note 10 , note 11) -86 -60 -80 - db db dynamic range (-60db output, a-weighted. note 10) 92 96 db s/n (a-weighted. note 10) 92 96 db interchannel isolation (note 10, note 12) 80 90 db interchannel gain mismatch (note 10, note 12) - 0.3 - db gain drift - 200 - ppm/ c load resistance (ac-lord; note 13) tvoutl/r, vcroutl/r, monoout 4.5 k ? load capacitance tvoutl/r, vcroutl/r, monoout 20 pf output voltage (note 13, note 14) 1.85 2 2.15 vrms power supply rejection (psr. note 15) - 50 db note 8. measured by audio precision system two cascade. note 9. output clips over ?2.5dbfs digital input. note 10. dac to tvout note 11. except vcroutl/vcroutl pins. note 12. between tvoutl and tvoutr with digital inputs 1khz/0dbfs. note 13. thd+n: -80db(min. at 2vrns), -60db(typ. at 3vrms). note 14. full-scale output voltage by dac (0dbfs). output voltage of dac scales with the voltage of vd1, stereo output (typ@0dbfs) = 2v rms vd1/5 when volume#0=volume#1=0db . the output must not exceed 3vrms. note 15. the psr is applied to vd1 with 1khz, 100mv.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 14 - filter characteristics (ta = 25 c; vp=11.4 12.6v, vd1=vd2=4.75 5.25v, vvd1=vvd2=vvd3=vvd4=4.75 5.25v; fs = 48khz; dem0 = ?1?, dem1 = ?0?) parameter symbol min typ max units digital filter passband 0.05db (note 16) -6.0db pb 0 - 24.0 21.77 - khz khz stopband (note 16) sb 26.23 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay (note 17) gd - 24 - 1/fs digital filter + lpf frequency response 0 20.0khz fr - 0.5 - db note 16. the passband and stopband frequencies scale with fs. e.g.) pb=0.4535fs (@ 0.05db), sb=0.546fs. note 17. the calculating delay time which occurred by digital filtering. this time is from setting the 16/18/24bit data of both channels to input register to the output of analog signal.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 15 - analog characteristics (sd video) (ta = 25 c; vp=12v, vd1=vd2=5v; vvd1 =vvd2=vvd3=vvd4=5v; vvol1/0= ?00?, unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.7 v chrominance bias voltage at output pin. 2.2 v r/g/b clamp voltage at output pin. 0.7 v pb/pr clamp voltage at output pin. 2.2 v gain input=0.3vp-p, 100khz 5.5 6 6.5 db vvol1/0= ?00? 5.5 6 6.5 db vvol1/0= ?01? 6.7 7.2 7.7 db vvol1/0= ?10? 7.7 8.2 8.7 db rgb gain input=0.3vp-p, 100khz vvol1/0= ?11? 8.6 9.1 9.6 db interchannel gain mismatch tvrc, tvg, tvb. input=0.3vp-p, 100khz -0.5 - 0.5 db frequency response input=0.3vp-p, c1=c2=0pf. 100khz to 6mhz. at 10mhz. at 27mhz. -1.0 -3 -40 0.5 -25 db db db group delay distortion at 4.43mhz with respect to 1mhz. 15 ns input impedance chrominance input (internally biased) 40 60 - k ? input signal f=100khz, distortion < 1.0%, gain=6db - - 1.5 vpp load resistance (note 18) 150 - - ? load capacitance c1 (note 18) c2 (note 18) 400 15 pf pf dynamic output signal f=100khz, distortion < 1.0% - - 3 vpp y/c crosstalk f=4.43mhz, 1vp-p input. among tvvout, tvrc, vcrvout and vcrc outputs. - -50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw= 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - +0.3 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - +0.6 - degree note 18. refer the figure 1. video signal output 75 ? 75 ? max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2 and load capacitance c1/c2.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 16 - analog characteristics (hd video) (ta = 25 c; vp=12v, vd1=vd2=5v; vvd1 =vvd2=vvd3=vvd4=5v; vvol1/0= ?00?, unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.7 v r/g/b clamp voltage at output pin. 0.7 v pb/pr clamp voltage at output pin. 2.2 v gain input=0.3vp-p, 100khz 5.5 6 6.5 db fl1/0,flpb1/0,flpr1/0= ?10? 100khz to 20mhz, at 30mhz. at 74.25mhz. -1.0 -2.5 -40 1.0 -25 db db db fl1/0,flpb1/0,flpr1/0= ?01? 100khz to 15mhz, at 54mhz. -1.0 -40 1.0 -25 db db frequency response input=0.3vp-p, c1=c2=0pf (note 18) fl1/0,flpb1/0,flpr1/0= ?00? 100khz to 6mhz, at 27mhz. -1.0 -40 0.5 -25 db db input signal f=100khz, distortion < 1.0%, gain=6db - - 1.5 vpp load resistance (figure 1) 150 - - ? load capacitance c1 (figure 1) c2 (figure 1) 400 10 pf pf dynamic output signal f=100khz, distortion < 1.0% - - 3 vpp differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. fl1/0,flpb1/0,flpr1/0= ?00? - +0.3 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. fl1/0,flpb1/0,flpr1/0= ?00? - +0.6 - degree
asahi kasei [AK4706] ms0507-e-00 2006/05 - 17 - switching characteristics (ta = 25 c; vp=11.4 12.6v, vd1=vd2=4.75 5.25v, vvd1=vvd2=vvd3=vvd4=4.75 5.25v; c l = 20pf) parameter symbol min typ max units master clock frequency 256fs: duty cycle 384fs: duty cycle fclk dclk fclk dclk 8.192 40 12.288 40 12.8 60 19.2 60 mhz % mhz % lrck frequency duty cycle fs duty 32 45 50 55 khz % audio interface timing bick period bick pulse width low pulse width high bick ? ? to lrck edge (note 19) lrck edge to bick ? ? (note 19) sdti hold time sdti setup time tbck tbckl tbckh tblr tlrb tsdh tsds 312.5 100 100 50 50 50 50 ns ns ns ns ns ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 20) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 khz s s s s s s s s s s ns reset timing pdn pulse width (note 21) tpd 150 ns note 19. bick rising edge must not occur at the same time as lrck edge. note 20. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. note 21. the AK4706 should be reset by pdn pin = ?l? upon power up. note 22. i 2 c is a registered trademark of philips semiconductors.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 18 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr serial interface timing
asahi kasei [AK4706] ms0507-e-00 2006/05 - 19 - thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn power-down timing
asahi kasei [AK4706] ms0507-e-00 2006/05 - 20 - operation overview 1. system reset and power-down options the AK4706 should be reset once by bringing pdn pin = ?l ? upon power-up. the AK4706 has several operation modes. the pdn pin, auto bit, dapd bit, mute bit and stby bit c ontrol operation modes as shown in table 1 and table 2. mode pdn pin auto bit stby bit mute bit dapd bit mode 0 ?l? * * * * full power-down 1 ?h? 1 * * * auto startup mode (default) 2 ?h? 0 1 1 * standby & mute 3 ?h? 0 1 0 * standby 4 ?h? 0 0 1 1 mute (dac power down) 5 ?h? 0 0 1 0 mute (dac operation) 6 ?h? 0 0 0 1 normal operation (dac power down & analog input) 7 ?h? 0 0 0 0 normal operation (dac operation) *: don?t care table 1. operation mode settings audio video output mode register control dac mclk, bick, lrck audio bias level video signal tvfb, tvsb vcrsb 0 full power-down not available power down not needed power down hi-z hi-z pull-down (2) 1 auto startup mode no video input available auto startup mode video input (3) active active (4) active active 2 standby & mute power down hi-z/ active 3 standby active 4 mute1 power 5 mute2 active needed down 6 normal operation (dac power down & analog input) power down not needed active (1) 7 normal operation (dac operation) active needed notes: (1) tvoutl/r are muted by vmute bit in the default state. (2) internally pulled down by 120kohm(typ) resistor. (3) video input to tvvin or vcrvin. (4) vcrc outputs 0v for termination. hd video output does not work. (hi-z default) table 2. status of each operation modes
asahi kasei [AK4706] ms0507-e-00 2006/05 - 21 - ? system reset and full power-down mode the AK4706 should be reset once by bringing pdn pin = ?l? upon power-up. pdn pin: power down pin ?h?: normal operation ?l?: device power down. ? auto startup mode when the pdn pin is set to ?h?, the AK4706 is in the auto startup mode. in this mode, all blocks except for the video detection circuit are powered down. once the video detecti on circuit detects video signal from tvvin pin or vcrvin pin, the AK4706 goes to the stand-by mode (both fast blanking and slow blanking are also fixed to vcr-tv loop-through) automatically and sends ?h? pulse via int pin. to exit the auto startup mode, set the auto bit to ?0?. the hd video outputs in the auto startup mode are disable at power-up. in this mode, hd video outputs are controlled as shown in table 3. auto bit (00h d3): auto startup bit (sd video output) ?1?: auto start up enable (default). ?0?: auto startup disable (manual startup). hdapw bit (0ah d5): auto st artup bit (hd video output) ?1?: auto startup enable. ?0?: auto startup disable (manual startup: default). auto bit hdapw bit hd video output 0 0 set by hdsw1/0, hdcp1/0 bit 0 1 hi-z 1 0 hi-z 1 1 set by hdsw1/0, hdcp1/0 bit after a video signal is detected. table 3. hd video output status the figure 2 shows an example of the system timing at auto startup mode. a uto startup enable pdn pin a udio out (dc) don?t care clock, data in tvvout, vcrvout active (loop-through) tvvin signal in no signal don?t care signal in no signal don?t care vcrvin signal in no signal don?t care don?t care active (loop-through) hi-z hi-z active (loop-through) (gnd) active (loop-through) no signal no signal hi-z low power mode low power mode low power mode hd video active hi-z hi-z active hi-z output ?0? (default) hdapw bit ?1? a uto bit ?1?(defaoult) figure 2.auto startup mode sequence
asahi kasei [AK4706] ms0507-e-00 2006/05 - 22 - ? dac power-down mode the internal dac block can be powered-down and switched to 1vrms analog input mode. when dapd bit =?1?, the zero-cross detection and offset calibration does not work. dapd bit (00h d2): dac power-down bit. ?1?: dac power-down. analog-input mode. #52 pin: mclk ? unused pin. this pin should be open. #53 pin: bick ? dacr. rch analog input. #54 pin: sdti ? unused pin. this pin should be open. #55 pin: lrck ? dacl. lch analog input. ?0?: dac operation. (default) ? standby mode when the auto bit = mute bit = ?0? and the stby bit = ?1?, the AK4706 is forced into tv-vcr loop through mode. in this mode, the sources of tvoutl/r and monoout pins are fixed to vcrinl/r pins; the sources of vcroutl/r are fixed to tvinl/r pins respectively. the gain of volume #1 is fixed to 0db. all register values themselves are not changed by stby bit = ?1?. stby bit (00h d0): standby bit. ?1?: standby mode. (default) ?0?: normal operation. ? mute mode (bias-off mode. 00h: d1) when the mute bit = ?1?, the bias voltage on the audio output goes to gnd level. bringing mute bit to ?0? changes this bias voltage smoothly from gnd to vp/2 by 2sec(typ.). this removes the huge click noi se related the sudden change of bias voltage at power-on. the change of mute bit from ?1? to ?0? also makes smooth transient from vp/2 to gnd by 2sec(typ). this removes the huge click noise related the sudden change of bias voltage at power-off. mute bit: bias-off bit. ?1?: set the audio bias to gnd. (default) ?0?: normal operation ? normal operation mode to use the dac or change analog switches, set the auto bit, dapd bit, mute bit and stby bit to ?0?. the dac is in power-down mode until mclk and lrck are input. the ak 4706 is in power-down mode until mclk and lrck are input. the figure 2 shows an example of the system timing at the power-down and power-up by pdn pin.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 23 - ? typical operation sequence the figure 3 shows an example of the system timing. pdn p in gd d/a out (internal) (1) tv out ?1? (default) stby bit ?0? ?1? don?t care (2) clock in normal operation don?t care (2) don?t care data in don?t care ?0? gd (1) ?0? dac tv-source select vcr in vcr in ?1? (default) mute bit ?0? ?stand-by? vcr in (3) vcr in fixed to vcr in(loop-through) ?1? ?0? ?stand-by? ?mute? audio data ?1? (default) ?1? (default) a uto bit ?0? hi-z hd video normal operation(4) hi-z output id figure 3. typical operating sequence (except auto setup mode) notes: (1) the analog output corresponding to the digital input has a group delay, gd. (2) the external clocks (mclk, bick and lrck) can be stopped in standby mode. (3) mute the analog outputs externally if c lick noise(3) adversely affects the system. (4) the hdsw1/0, hdcp1/0 bits set hd video outputs.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 24 - 2. audio block ? system clock the external clocks required to operate the dac section of AK4706 are mclk, lrck and bick. the master clock (mclk) corresponds to 256fs or 384fs. mclk frequency is automatically detected, and the internal master clock becomes 256fs. the mclk should be synchronized with l rck but the phase is not critical. table 4 illustrates corresponding clock frequencies. all external clocks (mclk, bick and lrck) should always be present whenever the dac section of AK4706 is in the normal operating mode (stby bit = ?0? and dapd bit = ?0?). if these clocks are not provided, the AK4706 may draw excess current because the de vice utilizes dynamically refre shed logic internally. the dac section of AK4706 should be reset by stby bit = ?0? after threse clocks are provided. if the external clocks are not present, place the AK4706 in power-down mode (stby bit = ?1?). after exiting reset at power-up etc., the AK4706 remains in power-down mode until mclk and lrck are input. lrck mclk bick fs 256fs 384fs 64fs 32.0khz 8.1920mhz 12.2880mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 3.0720mhz table 4. system clock example ? audio serial interface format (00h: d5-d4) data is shifted in via the sdti pin using bick and lrck inputs. the dif0 and dif1 bits can select four formats in serial mode as shown in table 5. in all modes, the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 2 can also be used for 16 msb justified formats by zeroing the unused two lsbs. mode dif1 dif0 sdti format bick figure 0 0 0 16bit lsb justified 32fs figure 4 1 0 1 18bit lsb justified 36fs figure 4 2 1 0 24bit msb justified 48fs figure 5 3 1 1 24bit i 2 s compatible 48fs or 32fs figure 6 default table 5. audio data formats
asahi kasei [AK4706] ms0507-e-00 2006/05 - 25 - sdti lrck bick 14 0 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb sdti mode 1 17:msb, 0:lsb 15 14 0 15 14 0 don?t care don?t care 17 16 17 16 lch data rch data 15 15 figure 4. mode 0,1 timing lrck bick sdti 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 22 1 0 don?t care 23 16 17 figure 5. mode 2 timing lrck bick sdti 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 22 1 0 don?t care 23 17 figure 6. mode 3 timing
asahi kasei [AK4706] ms0507-e-00 2006/05 - 26 - ? de-emphasis filter (00h: d7-d6) a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is controlled by the dem0 and dem1 bits. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 6. de-emphasis filter control ? switch control the AK4706 has switch matrixes designed primarily for scart routing. those are controlled via the control register as shown in table 7, table 8 and table 9 (refer to the block diagram). (01h: d1-d0) tv1 tv0 source of tvoutl/r 0 0 dac 0 1 vcrin (default) 1 0 mute 1 1 (reserved) table 7. tvout switch configuration (01h: d2-d0) vol tv1 tv0 source of monoout 0 0 0 dac (l+r)/2 0 0 1 dac (l+r)/2 0 1 0 dac (l+r)/2 bypass the volume #1 0 1 1 (reserved) 1 0 0 dac (l+r)/2 1 0 1 vcrin (l+r)/2 through the volume #1 1 1 0 mute 1 1 1 (reserved) table 8. monoout switch configuration (01h: d5-d4) vcr1 vcr0 source of vcroutl/r 0 0 dac 0 1 tvin (default) 1 0 mute 1 1 output of volume #1 table 9. vcrout switch configuration
asahi kasei [AK4706] ms0507-e-00 2006/05 - 27 - ? volume control #0, #2 (4-level volume) the AK4706 has a 4-level volume control (volume #0, #2) as shown in table 10 and table 11. the volume reflects the change of register value immediately. (03h: d4-d3) dvol1 dvol0 volume #0 gain output level (typ) 0 0 0db 2vrms (with 0dbfs input & volume #1=0db.) 0 1 -6db 1vrms (with 0dbfs input & volume #1=0db.) 1 0 +2.44db 2.65vrms (with 0dbfs input & volume #1=0db.) 1 1 +4db 2vrms (with ?10dbfs input & volume #1=+6db. clips over ?2.5dbfs digital input.) table 10. volume #0 (at dapd bit =?0?. dac mode) (03h: d4-d3) dvol1 dvol0 volume #2 gain output level (typ) 0 0 +6db 2vrms (with 1vrms input & volume #1=0db.) 0 1 0db 1vrms (with 1vrms input & volume #1=0db.) 1 0 (reserved) - 1 1 (reserved) - table 11. volume #2 (at dapd bit =?1?. analog input mode.)
asahi kasei [AK4706] ms0507-e-00 2006/05 - 28 - ? volume control #1 (main volume) the AK4706 has main volume control (volume #1) as shown in table 12. (02h: d5-d0) l5 l4 l3 l2 l1 l0 gain 1 0 0 0 1 0 +6db 1 0 0 0 0 1 +4db 1 0 0 0 0 0 +2db 0 1 1 1 1 1 0db (default) ? ? ? ? ? ? ? 0 0 0 0 0 1 -60db 0 0 0 0 0 0 mute note: the output must not exceed 3vrms. table 12. volume #1 when the mod bit = ?1?(default), changing levels don?t ha ve pop noise. mdt1-0 bits select the transition time (see table 13). when the new gain value 1eh(-2db) is written to gain resistor while the actual (stable) gain is 1fh(0db), the gain changes to 1eh(-2db) within the transition time select ed by mdt1-0 bits. the AK4706 compares the actual gain to the value of gain register after finishing the transition time, and re-changes the actual gain to new resister value within the transition time if the register value is different from the act ual gain when compared. when the mod bit = ?0 ? then there is no transition time and the gain changes immediately. this change may cause a click noise. a ctual gain gain register transition time (256/fs to 2048/fs. pop free.) 1fh 1eh 1dh 1eh 1fh 1dh wr [gain=1eh] wr [gain=1ch] wr [gain=1dh] 1ch 1ch compare compare compare (to 1eh) (to 1dh) (to 1ch) figure 7. volume change operation (mod bit = ?1?) mdt1 mdt0 transition time 0 0 256/fs 0 1 512/fs 1 0 1024/fs 1 1 2048/fs (default) table 13. volume transition time
asahi kasei [AK4706] ms0507-e-00 2006/05 - 29 - 3. video block ? video switch control the AK4706 has switches for tv, vcr and rf modulator. each switches can be controlled via registers independently. when auto bit = ?1? or stby bit = ?1?, these switch setting are ignored and set to fixed configuration (loop-through mode). please refer the auto setup mode and standby mode. (04h: d2-d0) mode vtv2-0 bit source of tvvout pin source of tvrc pin source of tvg pin source of tvb pin shutdown 000 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs+rgb or encoder ypbpr 001 encv pin (encoder cvbs or y) encrc pin (encoder red,c or pb) encg pin (encoder green or y) encb pin (encoder blue or pr) encoder y/c 1 010 encv pin (encoder y) encrc pin (encoder c) (hi-z) (hi-z) encoder y/c 2 011 ency pin (encoder y) encc pin (encoder c) (hi-z) (hi-z) vcr (default) 100 vcrvin pin (vcr cvbs or y) vcrrc pin (vcr red,c or pb) vcrg pin (vcr green or y) vcrb pin (vcr blue or pr) tv cvbs 101 tvvin pin (tv cvbs) (hi-z) (hi-z) (hi-z) (reserved) 110 - - - - (reserved) 111 - - - - (refer note 23, note 24) table 14. tv video output (04h: d5-d3) mode vvcr2-0 bit source of vcrvout pin source of vcrc pin shutdown 000 (hi-z) (hi-z) encoder cvbs or y/c 1 001 encv pin (encoder cvbs or y) encrc pin (encoder c) encoder cvbs or y/c 2 010 ency pin (encoder cvbs or y) encc pin (encoder c) tv cvbs (default) 011 tvvin pin (tv cvbs) (hi-z) vcr 100 vcrvin pin (vcr cvbs) vcrrc pin (vcr c) (reserved) 101 - - (reserved) 110 - - (reserved) 111 - - (refer note 23) table 15. vcr video output
asahi kasei [AK4706] ms0507-e-00 2006/05 - 30 - (04h: d7-d6) mode vrf1-0 bit source of rfv pin encoder cvbs1 00 encv pin. (encoder cvbs) encoder cvbs2 01 encg pin. (encoder cvbs) (note 24) vcr (default) 10 vcrvin pin. (vcr cvbs) shutdown 11 (hi-z) table 16. rf video output note 23. when input the video si gnal via encrc pin or vcrrc pin, se t clamp1-0 bits respectively. note 24. when vtv2-0 bit =?001?, tvg bit =?1? and vrf1-0 bit =?01?, rfv pin output is same as tvg pin output (encoder g). ? video output control (05h: d6-d0) each video outputs can be set to hi-z individually via cont rol registers. these setting are ignored when the auto bit = ?1?. when the cio bit = ?1?, the vcrc pin outputs 0v even if the vcrc bit = ?0?. when the cio bit = ?0?, the vcrc pin follows the setting of vcrc bit. please refer the ?red/chroma bi-directional control for vcr scart?. tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control tvfb: tvfb output control 0: hi-z (default) 1: active. ? red/chroma bi-directional control for vcr scart (05h: d7, d5) the AK4706 supports the bi-directional red/chroma signal on the vcr scart. (AK4706) vcrrc pin vcrc pin vcr scart 75 0.1u (cio bit & vcrc bit) #15 pin figure 8. red/chroma bi-directional control
asahi kasei [AK4706] ms0507-e-00 2006/05 - 31 - cio vcrc state of vcrc pin 0 0 hi-z (default) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 17 red/chroma bi-directional control ? rgb video gain control (06h: d1-d0) vvol1-0 bits set the rgb video gain. vvol1 vvol0 gain output level (typ. @input=0.7vpp) 0 0 +6db 1.4vpp (default) 0 1 +7.2db 1.6vpp 1 0 +8.2db 1.8vpp 1 1 +9.1db 2.0vpp table 18. rgb video gain control ? clamp and dc-restore circuit control (06h: d7-d2, 0ah: d3) each cvbs and y input has the sync tip clamp circuit. the dc-restore circuit has two clamp voltages 0.7v(typ) and 2.2v(typ) to support both rgb and ypbpr signal. they correspond to 0.35v(typ) and 1.1v(typ) at the scart connector when matched by 75ohm resistors. the clamp1, clamp0 and clampb bits se lect the input circuit for encrc pin (encoder red/chroma), encb pin (encoder blue), vcrrc pin (vcr red/chroma) and vcrb pin (vcr blue) respectively. vclp1-0 bits select the sync source of dc- restore circuit. clampb clamp0 vcrrc input circuit vcrb i nput circuit vcrg input circuit note 0 0 dc restore (0.7v) dc restore (0 .7v) dc restore (0.7v) for rgb 0 1 biased dc restore (0.7v) dc restore (0.7v) for y/c default 1 0 dc restore (2.2v) dc restore (2.2v) sync tip clamp (0.7v) for ypbpr 1 1 (reserved) (reserved) (reserved) table 19. dc-restore control for vcr input clampb clamp1 encrc input circ uit encb input circuit note 0 0 dc restore (0.7v) dc re store (0.7v) for rgb default 0 1 biased dc restore (0.7v) for y/c 1 0 dc restore (2.2v) dc restore (2.2v) for ypbpr 1 1 (reserved) (reserved) table 20. dc-restore control for encoder input clamp2 encg input circuit note 0 dc restore (0.7v) for rgb default 1 sync tip clamp (0.7v) for ypbpr note: when the vtv2-0 bits = ?001?, tvg bit =?1? and vclp2- 0 bits = ?011?, sync tip is selected even if the clamp2 bit = ?0?. table 21. dc-restore control for encoder green/y input
asahi kasei [AK4706] ms0507-e-00 2006/05 - 32 - vclp2-0: dc restore source control vclp2 vclp1 vclp0 sync source of dc restore 0 0 0 encv (default) 0 0 1 ency 0 1 0 vcrvin 0 1 1 encg 1 0 0 vcrg 1 0 1 (reserved) 1 1 0 (reserved) 1 1 1 (reserved) note: when the auto bit = ?1?, the source is fixed to vcrvin. table 22. dc-restore source control ? hd video control (0ah: d7-d6, d1-d0) fly1/0, flpb1/0, flpr1/0 bits a nd hdsw1/0, hdcp1/0 bits set the hd video switch and filter response. hdsw1 hdsw0 hdcp1 hdcp0 hd ypbpr ? rgb control 0 0 0(default) 0(default) /1 ypbpr. ency2 = 0.7v clamp, encpb = 2.2v dc-restore, encpr = 2.2v dc-restore. (ency2= sync source only for encpb, encpr) 0 0 1 0 rgb. ency2 = 0.7v clamp, encpb = 0.7v dc-restore, encpr = 0.7v dc-restore. (ency2= sync source only for encpb, encpr) 0 0 1 1 rgb. ency2 = 0.7v dc-restore, encpb = 0.7v dc-restore, encpr = 0.7v dc-restore. sync source = encv 0 1 * * encg, encb, encr follow clampb, 2, 1 1 0 * * vcrg, vcrb, vcrrc follow clampb, 0. vcrg follow vcrrc circuit. 1(default) 1(default) * * hi-z table 23. hd video switch control (3ch common) input output fly1/ flpb1/flpr1 bit fly0/ flpb0/flpr0 bit lfp response 0 0 6mhz lpf (default) 0 1 12mhz lpf 1 0 30mhz lpf 1 1 (reserved) table 24. hd video filter control (3ch independent)
asahi kasei [AK4706] ms0507-e-00 2006/05 - 33 - 4. blanking control, s1/s2 dc control when the sdc bit= ?0?, the AK4706 supports fast blanking signals and slow blanking (function switching) signals for tv/vcr scart. when the sdc bit= ?1?, the AK4706 supports s1/s2 mode. sdc bit: scart-s1/s2 control 0: scart fast/slow blanking mode 1: s1/s2 mode ? input/output control for fast/slow blanking fb1-0: tv fast blanking output control (0ah: d4, 07h: d1-d0) input output sdc bit fb1 bit fb0 bit tvfb pin output level 0 0 0 <0.4v (default) 0 0 1 4v< 0 1 0 same as vcr fb input (4v/0v) 0 1 1 (reserved) 1 0 0 <0.4v 1 0 1 1.55v to 2.4v 1 1 0 same as vcr fb input (5v/2.2v/0v) 1 1 1 3.5v< (note: load resistance is min.150ohm for sdc bit =?0?, min.100kohm for sdc bit =?1?) table 25. tv fast blanking output sbt1-0: tv slow blanking output control (0ah: d4, 07h: d3-d2) input output sdc bit sbt1 bit sbt0 bit tvsb pin output level 0 0 0 <2v (default) 0 0 1 5v to 7v 0 1 0 (reserved) 0 1 1 10v< 1 0 0 <0.4v 1 0 1 1.55v to 2.4v 1 1 0 (reserved) 1 1 1 3.5v< (note: load resistance is min.10kohm for sdc bit =?0?, min.100kohm for sdc bit =?1?) table 26. tv slow blanking output sbv1-0: vcr slow blanking output control (07h: d5-d4) sbv1 sbv0 vcrsb pin output level 0 0 <2v (default) 0 1 5v to 7v 1 0 (reserved) 1 1 10v< (note: load resistance is min.10kohm) table 27. vcr slow blanking output
asahi kasei [AK4706] ms0507-e-00 2006/05 - 34 - sbio1-0: tv/vcr slow blanking i/o control (07h: d7-d6) sbio1 sbio0 vcrsb pin direction tvsb pin direction 0 0 output (controlled by sbv1,0) output (controlled by sbt1,0) (default) 0 1 (reserved) (reserved) 1 0 input (stored in svcr1,0) output (controlled by sbt1,0) 1 1 input (stored in svcr1,0) output (same output as vcr sb) table 28. tv/vcr slow blanking i/o control
asahi kasei [AK4706] ms0507-e-00 2006/05 - 35 - 5. monitor options and int function ? monitor options (08h: d7, d5, d2-d0) the AK4706 has several detection functions. svcr1-0 bits, fvcr bit, vcmon bit and tvmon bit reflect the input dc level of vcr slow blanking, the input dc level of vcr fast blanking and signals input to tvvin or vcrvin pins. sdc bit: scart-s1/s2 control 0: scart fast/slow blanking mode 1: s1/s2 mode svcr1-0 bit: vcr slow blanking status monitor svcr1-0 bits reflect the voltage at vcrsb pin only when the vcrsb pin is in the input mode. when the vcrsb is in the output mode, svcr1-0 hold previous value. input output sdc bit vcrsb pin input level svcr1 bit svcr0 bit 0 < 2v 0 0 0 4.5 to 7v 0 1 0 (reserved) 1 0 0 9.5< 1 1 1 < 0.4v 0 0 1 1.4 to 2.4v 0 1 1 (reserved) 1 0 1 3.5v< 1 1 note: when sdc bit =?0?, vcrsb pin is connected to a internal pull-down resistor(120k ? @typ). table 29. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. input output sdc bit vcrfb pin input level fvcr1 bit fvcr0 bit 0 <0.4v 0 0 0 1 v< 0 1 0 (reserved) 0 0 0 (reserved) 0 0 1 < 0.4v 0 0 1 1.4 to 2.4v 0 1 1 (reserved) 1 0 1 3.5v< 1 1 table 30. vcr fast blanking monitor (typical threshold is 0.7v)
asahi kasei [AK4706] ms0507-e-00 2006/05 - 36 - vcmon: vcrvin pin video input monitor (mcomn bit =?1?), tvvin pin or vcrvin pin video input monitor (mcomn bit = ?0?) 0: no video signal detected. 1: detects video signal. tvmon: tvvin pin video input monitor (active when mcomn bit = ?1?) 0: no video signal detected. 1: detects video signal. mcomn (09h d7) tvvin signal* vcrvin signal* tvmon (08h d4) vcmon (08h d3) 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 *: ?0? is no signal. ?1? is signal input table 31. tv/vcr monitor function
asahi kasei [AK4706] ms0507-e-00 2006/05 - 37 - ? int function and mask options (09h: d7, d4-d1) changes of the 08h status can be monitored via the int pin. the int pin is the open drain output and goes ?l? for 2 sec(typ.) when the status of 08h is changed. this pin should be connected to vd2 (typ. 5v) through 10kohm resistor. mtv bit, mvc bit, mcomn bit, mfvcr bit and msvcr bit control the reflection of the status change of these monitors onto the int pin from report to prevent to masks each monitor. AK4706 r=10k ? int vd2 up figure 9. int pin mvc: vcmon mask. refer table 33 mtv: tvmon mask. refer table 32 mcomn: refer table 31 auto (00h d3) tvmon (08h d4) mtv (09h d4) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z 1 change 0 generates ?l? pulse 1 change 1 generates ?l? pulse table 32. tv monitor mask auto (00h d3) vcmon (08h d3) mvc (09h d3) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z 1 change 0 generates ?l? pulse 1 change 1 generates ?l? pulse table 33. vcr monitor mask mfvcr: fvcr monitor mask. 0: change of mfvcr is reflected to int pin. (default) 1: change of mfvcr is not reflected to int pin. msvcr: svcr1-0 monitor mask 0: change of svcr1-0 is reflected to int pin. (default) 1: change of svcr1-0 is not reflected to int pin.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 38 - 6. control interface i 2 c-bus control mode 1. write operations figure 10 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 16). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the AK4706, the AK4706 generates the acknowledge and the opera tion is executed. the master must generate the acknowledge-related clock pulse and release the sda line (h igh) during the acknowledge clock pulse (figure 17). a ?1? for r/w bit indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the address for control registers of the AK4706. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 12). the data after the second byte contain control data. the format is msb first, 8bits (figure 13). the AK4706 generates an acknowledge after each byte has been r eceived. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 16). the AK4706 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the AK4706 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after the receipt of each data, the internal address counter is incremented by one, and the ne xt data is taken into next address au tomatically. if the address exceeds 0bh prior to generating the stop condition, the addr ess counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 18) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 10. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 11. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 12. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 13. byte structure after the second byte
asahi kasei [AK4706] ms0507-e-00 2006/05 - 39 - 2. read operations set r/w bit = ?1? for read operations. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of termin ating the write cycle after the receipt th e first data word. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 09h prior to generating the stop conditi on, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4706 supports two basic read operations : current address read and random read. 2-1. current address read the AK4706 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the AK4706 generates an acknowledge, transmits 1byte data which address is set by the in ternal address counter and increments the internal address counter by 1. if the master does not ge nerate an acknowledge to the data but generate the stop condition, the AK4706 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 14. current address read 2-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, slave address(r/w=?0?) and then the register address to r ead. after the register?s address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the AK4706 generates an acknowledge, 1-byte data and increments the internal addr ess counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4706 disc ontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 15. random address read
asahi kasei [AK4706] ms0507-e-00 2006/05 - 40 - scl sda stop condition start condition s p figure 16. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 17. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 18. bit transfer on the i 2 c-bus
asahi kasei [AK4706] ms0507-e-00 2006/05 - 41 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control dem1 dem0 dif1 dif0 auto dapd mute stby 01h switch vmute 0 vcr1 vcr0 mono vol tv1 tv0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 03h zerocross 0 vmono 1 dvol1 dvol0 mod mdt1 mdt0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 05h video output enable cio tvfb vcrc vcrv tvb tvg tvr tvv 06h video volume/clamp clampb vclp1 vclp0 clamp2 clamp1 clamp0 vvol1 vvol0 07h s/f blanking control sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 08h s/f blanking monitor 0 0 fvcr1 tvmon vcmon fvcr0 svcr1 svcr0 09h monitor mask mcomn 0 mtv mvc mfvcr msvcr 0 0ah hd switch hdcp1 hdcp0 hdapw sdc vclp2 0 hdsw1 hdsw0 0bh hd filter 0 0 flpr1 flpr0 flpb1 flpb0 fly1 fly0 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn pin =?h?, all registers can be accessed. do not write any data to the register over 0bh.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 42 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control dem1 dem0 dif1 dif0 auto dapd mute stby r/w r/w default 0 1 1 1 1 0 1 1 stby: standby control 0: normal operation 1: standby mode (default) dac: powered down and timings are reset. gain of volume#1: fixed to 0db source of tvout: fixed to vcrin source of vcrout: fixed to tvin source of monoout: fixed to vcrin source of tvvout: fixed to vcrvin (or hi-z) source of tvrc: fixed to vcrrc (or hi-z) source of tvg: fixed to vcrg (or hi-z) source of tvb: fixed to vcrb (or hi-z) source of tvfb: fixed to vcrfb (or hi-z) source of tvsb: fixed to vcrsb source of vcrvout: fixed to tvvin (or hi-z) source of vcrc: fixed to hi-z or vss (controlled by cio bit) mute: audio output control 0: normal operation 1: all audio outputs to gnd (default) dapd: dac power down control 0: normal operation (default). 1: dac power down. when dapd bit = ?1?, the soft transition for volume does not work. auto: auto startup bit 0: auto startup disable (manual startup). 1: auto startup enable (default). when the sbio1bit = ?1?(default= ?0?), the change of auto bit may cause a ?l? pulse on int pin. dif1-0: audio data interface format control 00: 16bit lsb justified 01: 18bit lsb justified 10: 24bit msb justified 11: 24bit i 2 s compatible (default) dem1-0: de-emphasis response control 00: 44.1khz 01: off (default) 10: 48khz 11: 32khz
asahi kasei [AK4706] ms0507-e-00 2006/05 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch vmute 0 vcr1 vcr0 mono vol tv1 tv0 r/w r/w default 1 0 0 1 0 1 0 1 tv1-0: tvoutl/r pins source switch 00: dac 01: vcrinl/r pins (default) 10: mute 11: (reserved) vol: monoout pin source switch 0: bypass the volume (fixed to dac out) 1: through the volume (default) mono: mono select for tvoutl/r pins 0: stereo. (default) 1: mono. (l+r)/2 vcr1-0: vcroutl/r pins source switch 00: dac 01: tvinl/r pins (default) 10: mute 11: volume #1 output vmute: mute switch for volume #1 0: normal operation 1: mute the volume #1 (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 r/w r/w default 0 0 0 1 1 1 1 1 l5-0: volume #1 control those registers control both lch and rch of volume #1. 111111 to 100011: (reserved) 100010: volume gain = +6db 100001: volume gain = +4db 100000: volume gain = +2db 011111: volume gain = +0db (default) 011110: volume gain = -2db ... 000011: volume gain = -56db 000010: volume gain = -58db 000001: volume gain = -60db 000000: volume gain = mute
asahi kasei [AK4706] ms0507-e-00 2006/05 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h zerocross 0 vmono 1 dvol1 dvol0 mod mdt1 mdt0 r/w r/w default 0 0 1 0 0 1 1 1 mdt1-0: the control of volume transition time (typ) 00: 256/fs 01: 512/fs 10: 1024/fs 11: 2048/fs (default) mod: soft transition enable for volume #1 control 0: disable. the volume value changes immediat ely without soft transition. 1: enable (default) the volume value changes with soft transition. this function is disabled when stby bit or dapd bit = ?1?. dvol1-0: volume #0/volume #2 control. refer the table 10 and table 11 vmono: mono select for vcroutl/r pins 0: stereo. (default) 1: mono. (l+r)/2
asahi kasei [AK4706] ms0507-e-00 2006/05 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 r/w r/w default 1 0 0 1 1 1 0 0 vtv2-0: selector for tv video output refer the table 14. vvcr2-0: selector for vcr video output refer the table 15 vrf1-0: selector for rfv pin output refer the table 16. addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable cio tvfb vcrc vcrv tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control (refer the table 17) tvfb: tvfb output control 0: hi-z (default) 1: active. when the cio pin = ?1?, the vcrc pin is connected to gnd even if vcrc= ?0?. when the cio pin = ?0?, the vcrc pin follows the setting of vcrc bit. cio: vcrc pin i/o control refer the table 17.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video volume clampb vclp1 vclp0 clam p2 clamp1 clamp0 vvol1 vvol0 r/w r/w default 0 0 0 0 0 1 0 0 vvol1-0: rgb video gain control 00: +6db (default) 01: +7.2db 10: +8.2db 11: +9.1db clampb, clamp2-0: clamp control. refer the table 19, table 20 and table 21. vclp1-0: dc restore source control 00: encv pin (default) 01: ency pin 10: vcrvin pin 11: (reserved) when the auto bit = ?1?, the s ource is fixed to vcrvin pin. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking sbio1 sbio0 sb v1 sbv0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking output control (for tvfb pin) 00: 0v (default) 01: 4v 10: follow vcr fb input (4v/0v) 11: (reserved) sbt1-0: tv slow blanking output control (for tvsb pin. load resistance is min.10kohm.) 00: <2v (default) 01: 5v to 7v 10: (reserved) 11: 10v< sbv1-0: vcr slow blanking output control (for vcrsb pin. load resistance is min.10kohm) 00: <2v (default) 01: 5v to 7v 10: (reserved) 11: 10v< sbio1-0: tv/vcr slow blanking i/o control (refer the table 28) addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h monitor 0 0 fvcr1 tvmon vcmon fvcr0 svcr1 svcr0 r/w read default 0 0 0 0 0 0 0 0 svcr1-0, fvcr1-0: vcr fast blanking/slow blanking monitor refer table 29, table 30. vcmon, tvmon: vcr/tv video input monitor refer table 31.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 47 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h monitor mask mcomn 0 0 mtv mvc mfvcr msvcr 0 r/w r/w default 0 0 0 0 1 0 0 0 msvcr: svcr1-0 monitor mask. 0: the int pin reflects the cha nge of svcr1-0 bits. (default) 1: the int pin does not reflect the change of svcr1-0 bit. mfvcr: fvcr monitor mask. 0: the int pin reflects the cha nge of mfvcr bit. (default) 1: the int pin does not reflect the change of mfvcr bit. mvc, mtv: vcr/tv monitor mask refer the table 32, table 33. mcomn : monitor mask option refer table 31. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah hd switch hdcp1 hdcp0 hdapw sdc vclp2 0 hdsw1 hdsw0 r/w r/w default 0 0 0 0 0 0 1 1 hdsw1-0, hdcp1-0: hd video switch. refer table 23. hdapw: auto startup bit (hd video output) 1: auto startup enable. 0: auto startup disable (manual startup: default). sdc: scart-s1/s2 dc control refer table 25, table 26 table 29 and table 30. vclp2: dc restore source control refer table 22 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh hd filter 0 0 flpr1 flpr0 flpb1 flpb0 fly1 fly0 r/w r/w default 0 0 0 0 0 0 0 0 fly1-0, flpb1-0, flpr1-0: hd video filter control refer table 24.
asahi kasei [AK4706] ms0507-e-00 2006/05 - 48 - system design AK4706 + 10u 0.1u a nalog 12v a nalog ground digital ground 10k 10k mpeg decoder hdy 1 hdpr 2 hdpb 3 vvd3 4 rfv 5 vcrvout 6 tvfb 7 vcrc 8 vvss2 9 tvvout 10 vvd2 11 tvrc 12 tvg 13 tvb 14 vvss1 15 refi 16 64 nc vvss3 nc vvd4 nc vvss4 pdn sda scl lrck sdti bick mclk vd2 vd1 17 vvd1 18 ency2 encpr encpb encb encg encrc encc encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb vss1 48 pvcom 47 dvcom 46 vp 45 monoout 44 tvoutl 43 tvout r 42 vcroutl 41 vcrout r 40 tvinl 39 tvin r 38 vcrinl 37 vcrin r 36 tvsb 35 vcrsb 34 int 33 vss2 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 + 10u 0.1u video 5v + 10u 0.1u 0.1u 10u + + 10u 0.1u + 10u 0.1u 0.1u 0.1u + 10u + 10u + 10u rf modulato r 75 + 10u + 10u 220k + 10u + 10u 0.1u a udio 5v 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 75 75 75 75 75 75 75 75 75 75 75 75 75 0.1u 75 0.1u 75 75 0.1u 0.1u 75 0.1u 75 75 75 75 75 75 75 video 5v tv scart 220k 220k 220k 300 300 300 0.1u 300 0.1u 300 0.1u 300 400 300 300 vcr scart 400 y/g out micro controller 300 video encoder pr/r out pb/b out figure 19. typical connection diagram
asahi kasei [AK4706] ms0507-e-00 2006/05 - 49 - ? grounding and power supply decoupling vd1-2, vp, vvd1-4, vss1-2 and vvss1-4 should be supplie d from analog supply unit with low impedance and be separated from system digital supply. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these pins to eliminate the effects of high frequency noise. the 0.1 f ceramic capacitors should be placed as near to vd (vd1-2, vp, vvd1-4) as possible. ? voltage reference dvcom and pvcom are signal ground of this chip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these vcom pins to eliminat e the effects of high frequency noise. no load current may be drawn from these vcom pins. all signals, especially clocks, should be kept away from these vcom pins in order to avoid unwanted coupling into the AK4706. ? analog audio outputs the analog outputs are also single-ended and centered on 5.6v(typ.). the output signal range is typically 2vrms (typ@vd1=5v). the internal switched-capacitor filter and continuous-time f ilter attenuate the noise generated by the delta-sigma modulator beyond the audio pass band. therefore, any external filte rs are not required for typical application. the output voltage is a positive full scale for 7fffffh (@ 24bit) and a negative full scale for 800000h (@24bit). the ideal output is 5.6v(typ.) for 000000h (@24bit). the dc voltage on analog outputs are eliminated by ac coupling. ? refi pin the refi pin is video current reference pin. this pin should be connected to vvd1 through a 10k ? 1% resistor externally as shown in the figure 20. no load current may be drawn from this pin. all signals, especially clocks, should be kept away from this pin in order to avoid unwanted coupling. AK4706 r=10k ? figure 20. refi pin
asahi kasei [AK4706] ms0507-e-00 2006/05 - 50 - ? external circuit example analog audio input pin tvinl/r vcrinl/r dacl/r 0.47 f 300ohm (cable) analog audio output pin monoout tvoutl/r vcroutl/r 10 f 300ohm total > 4.5kohm (cable) analog video input pin encv, ency, vcrvin, tvvin, encrc, encc, vcrrc, encg, vcrg, encb, vcrb, encpr , ency2, encpb 0.1 f 75ohm (cable) 75ohm analog video output pin tvvout, tvrc tvg, tvr, rfv vcrvout, vcrc, hdpr, hdy, hdpb max 400pf 75ohm 75ohm max 15pf (cable)
asahi kasei [AK4706] ms0507-e-00 2006/05 - 51 - slow blanking pin (sdc bit = ?0?) tvsb vcrsb max 3nf (with 400ohm) 400ohm (max 500ohm) min: 10k ohm (cable) fast blanking input pin (sdc bit = ?0?) vcrfb 75ohm (cable) 75ohm fast blanking output pin (sdc bit = ?0?) tvfb 75ohm 75ohm (cable) fast blanking output pin (sdc bit = ?0?) tvfb tvsb 10k +/-3kohm min: 100kohm (cable)
asahi kasei [AK4706] ms0507-e-00 2006/05 - 52 - package 12.00.3 0. 2 1 0. 0 5 0. 1 7 0. 0 5 12. 00. 3 1 16 17 32 33 48 49 64 0. 1 0 0. 5 1. 7 0 max 0. 1 0 0. 1 0 0 ~10 0. 4 5 0. 2 10. 0 64pi n lqfp( unit: mm ) 1. 4 0 0. 1 0 m 1. 0 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate
asahi kasei [AK4706] ms0507-e-00 2006/05 - 53 - marking 1 akm AK4706vq xxxxxxx xxxxxxxx: date code identifier revision history date (yy/mm/dd) revision reason page contents 06/05/09 00 first edition important notice ? these products and their specificat ions are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any pat ent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulati ons of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system , and akm assumes no responsibility relating to any such use, except with the express written c onsent of the representative director of akm. as used here: (a) a hazard related device or system is one des igned or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expect ed to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform ma y reasonably be expected to result, whether directly or indirectly, in the lo ss of the safety or effectiveness of the device or system containing it, and which must therefor e meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who dist ributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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